About Me

Profile Image

I'm Vaishnav Prasad,

System Hardware Engineer (Design Verification) focused on high-performance, reliable SoCs. Experienced in functional verification, LPDDR4/4X memory bring-up, and custom ISA validation using Verilog, SystemVerilog, UVM, C/C++, and Python.

Strong background in digital design, embedded systems, and computer architecture — delivering optimized hardware solutions under tight timelines. Passionate about RISC-V, chiplets, and hardware/software co-design.

Download Resume

Work Experience

System Hardware Engineer – NXP Semiconductors (formerly Kinara AI)

Hyderabad, Telangana | June 2024 – Present

  • Developed SystemVerilog-based constrained-random verification for a reconfigurable processor.
  • Validated custom TIE load/store/move instructions via opcode and operand coverage tracking.
  • Root-caused instruction mismatches via waveform and ISS comparison.
  • Maintained automated regression infrastructure for coverage and test tracking.

Education

B.E. Electronics & Instrumentation

BITS Pilani, K.K. Birla Goa Campus | Oct 2020 – May 2024

Relevant Coursework: Computer Architecture, Digital & Analog VLSI, OS, OOPs, Network Programming, Microprocessor Programming & Interfacing.

Technical Skills

  • Languages: SystemVerilog, Verilog, UVM, C, C++, Python
  • Protocols: AXI4, UART
  • Tools: Questasim, Xilinx Vivado, Xtensa Xplorer

Projects

RISC-V CPU Core

Designed single-cycle and 5-stage pipelined RV32I CPU cores in Verilog with AXI4-Lite compatible memory modules.

Handwritten Digit Recognition on FPGA

Built FPGA-based MNIST digit recognition accelerator using UART and BlockRAM for parallel inference execution.

Display and VGA Core

Created VGA signal generator core in Verilog; validated using Python scripts for bit-accurate image reproduction.

Simple Adder Core using UART and BlockRAM

Implemented UART-based FPGA adder core with data storage in BlockRAM and serial PC communication.

Linux Kernel System Call & Device Driver

Added custom system call to Linux Kernel 5.4.0 and developed a power-aware display brightness driver.

Connect

📧 rkvaishnavp@gmail.com
🌐 rkvp.in
💼 linkedin.com/in/rkvaishnavp
💻 github.com/rkvaishnavp